Connect - Makefiles
Makefiles are made with the following general format:
- The target is what you are trying to make,
- the dependency indicates all of the files that the target depends on,
- and the rule dictates how it actually is compiled.
Download the tar file make.tar to access the examples for this module. Decompress the example files and directories in it by invoking the following command:
> tar xvf Makefile.tar
Try looking at the first example of a Makefile under the directory M1. Notice the general format as explained above. While in the directory type "make code" at the command line and the program will be compiled. Each rule will be executed. Notice that
cc -o code main.o code1.o code2.o code3.o
was the last rule to be executed since it is dependent on the other four. Now, go into code2.c and make some type of change in it, such as adding another space somewhere, etc. Then type
>make code
again at the command line prompt. Notice this time what the compiler does:
cc -c -o code2.o code2.c
cc -o code main.o code1.o code2.o code3.o
Above, we see that only code2.c was recompiled, and not all five. Since code2.c was the only file changed, and code2.o is the only target dependent on code2.c, those two targets were the only ones affected by the change, and they were the only ones that needed to be updated. This is very beneficial, especially with large programs written in numerous files. It can turn hours of recompiling into seconds.
In the next example, in the M2 directory, we've added two things to the Makefile. Since there is now a header file for each file, that means each .o file is now dependent on it. At the bottom we've added a new target called clean. Notice that clean doesn't have any dependecies, only a rule to remove all of the .o files and to remove the executable. If you are concerned about conserving space on your hard drive, you do not always need to keep the executable stored. Try making code, the same as before. Then, at the command line prompt, type
> make clean
Your directory will now look just as it did before you performed the make code.
The final example on Makefiles is in the directory M3. In this example we globally define which compiler is being used, which flags we want used and which libraries are being linked in. The advantage of creating a Makefile in this manner is that if you need to add/remove anything such as linking another library, you only have to do it in one place and not within each individual rule. First, you define what it is you want. For example, since we wanted to link in the math library, we called it LIBS. Defining it at the top of the code as:
LIBS = -lm
Then we just add $(LIBS) to the end (since libraries are linked at the end) of each rule. The $() tells the rule to look at the beginning of the Makefile for what it needs to add.
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